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NXP Semiconductors /MIMXRT1021 /PWM1 /FFILT0

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Interpret as FFILT0

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FILT_PER0FILT_CNT 0 (DISABLED)GSTR

GSTR=DISABLED

Description

Fault Filter Register

Fields

FILT_PER

Fault Filter Period
FILT_CNT

Fault Filter Count
GSTR

Fault Glitch Stretch Enable

0 (DISABLED): Fault input glitch stretching is disabled.

1 (ENABLED): Input fault signals will be stretched to at least 2 IPBus clock cycles.

Links

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Register License

Copyright 2016-2020 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data